Electronic Transaction Terminals/Readers

The AT91SO100/101, AT91SO50/51 and the AT91SO25 are a low-power, high-performance, SC100 32-bit micro controller based on the ARM® enhanced RISC architecture.

This new SC100 core allows the linear addressing of up to 1M bytes of code and data as well as a number of new functional and security features.

A 3-level instruction pipeline allows the performance of one instruction in a single clock cycle, the SC100 achieves throughputs close to 1 MIPS per MHz.
The SC100 processor employs a unique architectural strategy known as Thumb® a super reduced instruction set that is ideally suited for high volume applications with memory restrictions and applications where code density is an important factor.

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General

High-performance, Low-power 32-bit ARM®-SC100™ Enhanced RISC Architecture
Von Neumann Load / Store Architecture
Single 32-bit Data Bus for Instructions and Data
Memory Protection unit · Internal Oscillator (VFO) (up to 50 MHz)
ESD Protection to ± 2000V (± 6000V on the ISO interfaces)
Operating Ranges: 3.3V (+/- 10%)
Compliant with EMV Level 1, VISA PED, APACS, ZKA, Common Criteria (EAL4+), FINREAD

Memory

256 bits of Key Storage (battery backup) · 32K Bytes of internal ROM Memory (Bootstrap & Crypto library)
256K Bytes of Internal EEPROM, Including 128 OTP Bytes and 384-byte Bit-addressable Bytes
1 to 128-byte Program/Erase
2 ms Program, 2 ms Erase
Endurance: 100,000 Write/Erase Cycles at temperature of 25 degrees C
10 Years Data Retention
100K Bytes of Internal RAM (4KB Crypto RAM)
Up to 16M Bytes of External Memory (AT91SO100/101 only)

Peripherals

Page Unit to access External Memory Page (AT91SO100/101 only)
Static Memory Controller (AT91SO100/101 only)
Two ISO 7816 controllers with DC/DC (one of them can be multiplexed to address 4SAM).

The DC/DC converter AT83C26 is not included in the versions AT91SO100, AT91SO50 and AT91SO25.

The two ISO 7816 controllers are still available

USB 2.0 Full Speed (8 endpoints)
SPI Controller (up to 6Mbps) and Two Wire Interface
Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)
Triple Track Magstripe Logical Interface · 5 8-bit I/O Port Interface (LEDs, Keyboard, LCD, spare...)
Real Time Clock (RTC) with Alarm interrupt
System Timer including a 16-bit Counter, Watchdog and Second Counter
Six-channel 16-bit Timer/counter
2-level, 28-interrupt Controller
Hardware DES and Triple DES DPA Resistant
Hardware AES 128-192-256
Hardware SHA-1, SHA-256
True Random Number Generator (RNG)
Two CRC 16 Engines and one CRC 32 Engine (Compliant with ISO/IEC 3309)
AdvX - Advanced crypto multiplier for cryptography and authentication (includingRSA, DSA, Key Generation, ECC)

Security

Dedicated Hardware for Protection Against SPA/DPA Attacks Advanced Protection Against Physical Attack, Including Active Shield
Intrusion sensors (mesh and switches).
Environmental Protection Systems (Voltage, Frequency, UV and Temperature)
Secure Memory Management/Access Protection (MPU)
Real time clock and battery back up
Compliant with EMV standard, VISA PED and FINREAD